Data received in the form of parallel words of a variable width must be often converted to parallel words of a predetermined fixed width for data packing purposes, as it is known to be utilized for data recording or transmission. Known data packers utilize parallel-to-serial converters, followed by serial-to-parallel converters for conversion of parallel input words of one width to parallel output words of a different width. The serial data conversion utilizes a high frequency serial clock which may exceed the maximum operation frequency of most types of known logic circuitry. In addition, generation of the fast serial clock requires a phase locked loop for synchronization. Such additional circuitry increases the space requirement on the circuit board, as well as cost. For example the well known ECL type logic circuitry may satisfy the high frequency requirement, however it has low packing density on the circuit board or chip, and it also requires a relatively high current power supply. Therefore, the use of ECL logic in the known data packers is not practical where the overall circuit size, cost and/or power are limited. A further disadvantage is that it is relatively difficult to format the data into blocks when utilizing parallel-to-serial conversion because such formatting generally involves inserting additional bits into the serial bit stream, requiring another, higher rate serial clock and the use of high rate first-in, first-out data storage buffers.